1. Field of the Invention
The present invention relates to an IC test system for testing various functions of IC devices and more particularly to an IC test system for automatically calibrating timing errors occurred when a plurality of test signal pattern outputs or the outputs from an IC device under test are judged.
2. Description of the Prior Art
With the advancement of semiconductor integrated circuit technology, the tendency toward a higher density and a higher operation speed of an IC device has been accelerated, so that there have been increasing demands for IC test systems capable of increasing not only the number of pins of IC devices under test but also the test speed. At present, an IC test system which has 512 test pins and a test speed of the order of 100 MHz is available on the market. With the advancement of the operation speed of devices, there have been strong demands for the improvement of not only the test speed but also the test timing accuracy.
In general, an IC test system has hardware or pin electronics as one unit which has the capability of supplying a test signal pattern to each test pin and analyzing and judging the output results from an IC device under test. In order to define the rise and fall timing of a signal waveform in the case of the generation of a test signal pattern, two or four independent timing signals are required and furthermore a timing signal for defining a judging timing is also needed in a comparator which judges the output results from the IC device under test.
Pin electronics units which are assigned to individual test pins vary in characteristics from each other and the variations in power supply and ambient temperature result in time errors of the timing signals in respective pin electronics units. More particularly, the test pattern supply timing or the test result judging timing varies from one pin electronics unit to another. It follows, therefore, that, in order to realize a high degree of test accuracy, timing errors must be calibrated prior to IC tests.
In a conventional IC test system, a main controller with capability equivalent to that of a mini-computer controls the whole IC test system including a group of pin electronics units and the calibration of a timing error of the type described above is executed in series pin by pin. That is, a reference timing signal generator is provided as a time reference in the case of the timing error calibration and is connected to one pin electronics unit to be calibrated by sequentially switching such a pin electronics unit to execute the calibration in series pin by pin. For instance, a typical reference is made to "CONTINUAL AUTOCALIBRATION FOR HIGH TIMING ACCURACY", Ken Skala, Proc. IEEE Int'l Test Conference, pp. 111-116, November 1980 and especially to pp. 115-116 and FIG. 6.
The number of timing signals to be calibrated is in proportion to the number of timing signals applied to each pin and the number of test pins. For instance, in the case of a commercially available multi-pin tester (256 pins), the number of timing signals to be calibrated is in excess of 1000. With the increase in the number of test pins, the time required for executing a timing error calibration is increased and, for instance, when there exist 512 pins, it takes from 10 to 30 minutes to accomplish the calibration processing.
As described above, in the conventional IC test system, timing error calibration is executed only in series pin by pin and it takes a long time to complete the calibration for all the pins. This serial test processing causes a serious problem when it is required to improve the test efficiency in addition to the increased number of test pins. In addition to the problem that the time required for timing error calibration is increased in proportion to the increase in the number of test pins, the improvement of the test speed inevitably needs a high degree of accuracy and therefore a longer time is required for executing the timing error calibration more accurately.